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elan microelect ronics corp. n o. 12, innovation 1 st rd., science-based industrial park hsin chu city, taiwan, r.o.c. tel: (03) 5639977 fax: (03) 5630118 EM78P5840/41/42 8-bit micro-controller version 2.6
version history specification revision history version content efhp5830b 1.0 initial version efhp5840 2.0 1. change counter1 external input pin from pc2 to p94 2. modify p60, p61 to input/output io 3. remove p71 internal pull high function 4. modify control register initial value 5. remove 256 byte data ram 6. remove spi function 7. add irc and eric oscillator function 8. decrease stack from 16 to 8 9. add counter1 external source (from io pad) 10. remove counter2 2.1 1. add the relative of eric os cillating frequency and external r 2.2 1. add irc mode clk trimming control in code option. 2. modify port9 sink/driver current. 2.3 1. rename ?erc mode? to ?eric mode? 2. modify the relative between eric mode?s oscillating clk and the value of external resister. 2.4 1. change pin name from ?erci? to ?eric? 2. change the descript about cont reg bit7 2.5 1. remove crystal mode?s idle application 2. modify operating temperature 2.6 1. rename efh78p5840/41/42 ? EM78P5840/41/42 2. change irc frequency deviation from +/- 5% to +/- 10% relative to em785840?s rom-less, otp and mask: rom-less otp mask ice5830 EM78P5840 em78p5841 em78p 5842 em785840 em785841 em785842 table1: the relation between em78p5830 and EM78P5840 series: em78p5830 series EM78P5840 series package em78p5830cp em78p5830acp EM78P5840p 18 pin pdip em78p5830cm em78p5830acm EM78P5840m 18 pin sop em78p5830bp em78p5830abp em78p5841p 20 pin pdip em78p5830bm em78p5830abm em78p5841m 20 pin sop em78p5830fp em78p5830afp em78p5842p 24 pin pdip em78p5830fm em78p5830afm em78p5842m 24 pin sop
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 1 2004/11/10 v2.6 table2: the major differences between em78p5830 and EM78P5840 series: em78p5830 series EM78P5840 series cid ram 256 byte na eric mode na under 6m hz irc mode na 2m / 4m hz wdt source crystal or pll irc1 external cnt1 input na shared with p94 p71 pull high internal pull high external pull high /reset pin /reset only shared with p71 pllc pin pllc only shared with p70 and erci xin, xout crystal input shared with p60 and p61 table3: the major differences between ice5840, EM78P5840 and em785840: ice5840 EM78P5840 series em785840 series cid ram 1024 byte na na cid ram address auto +1 v na na cnt1 (**) 8 bit counter 8 bit counter 8 or 16 (shared with cnt2) bit counter cnt2 (**) v x v stack 12 8 8 ** cnt2 is only exist on EM78P5840/41/42 and em785840/41/42, cnt2 is un-support on ice5840. table4: differences between EM78P5840, em78p5841 and em78p5842: EM78P5840 em78p5841 em78p5842 pin count 18 20 24 pwm x 2 channel 2 channel io (max) 16 18 22 user application note (before using this chip, take a look at the followi ng description note, it incl udes important messages.) 1. there are some undefined bits in the registers. the values in these bits are unpredicted. these bits are not allowed to use. we use the symbol ?-? in the spec to recognize them. a fixed value must be write in some specific unused bits by software or some unpredicted wrong will occur. 2. you will see some names for the register bits definitions. some name will be appear very frequently in the whole spec. the following descri bes the meaning for the register?s definitions such as bit type, bit name, bit number and so on.
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 2 2004/11/10 v2.6 76543 2 10 rab7 rab6 bab5 rab4 rab2 rab0 r/w-0 r/w-0 r-1 r/w-1 r r/w bit type bit name bit number read/write (default value=0) read/write (default value=1) read only (w/o default value) read/write (w/o default value) page0 ra register name and its page - rab1 (undefined) not allowed to use r-0 read only (default value=0) read only (default value=1) 3. always set iocc page1 bit 0 = 1 otherwise pa rtial adc function cannot be used (in ice5830). 4. please do not switch mcu operation mode from nor mal mode to sleep mode directly. before into sleep mode, please switch mcu to green mode. 5. while switching main clock (regardless of high fr eq to low freq or on the other hand), adding 6 instructions delay (nop) is required. 6. offset voltage will effect adc ? s result, please refer to figure 19 to detail. 7. please do not connect unnecessary circuit on otp burner pins during burning the otp rom.
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 3 2004/11/10 v2.6 i. general description the EM78P5840 series are 8-bit risc type microprocesso r with low power, high speed cmos technology. there are 4kx13 bits electrical one time programmable read only memory (otp-r om) within it. it provides security bits and some one time programmable option bits to protect the otp memory code from any external access as well as to meet user?s options. this integrated single chip has an on_chip watchdog timer (wdt), program otp-rom, ram, programmable real time clock/counter, internal interrupt, power down mode, dual pwm (pulse width modulation), 8-channel 10-bit a/d converter and tri-state i/o. ii. feature cpu operating voltage : 2.2v~5.5v at main clk less then 3.58mhz. main clk(hz) under 3.58m 14.3m operating voltage(min) 2.2v 3.6v ?e 4k x 13 on chip electrical one time pr ogrammable read only memory (otp-rom) ?e 144 x 8 on chip general propose ram ?e up to 19 bi-directional and 3 input only general purpose i/o ?e 8 level stack for subroutine nesting ?e 8-bit real time clock/counter (tcc) ?e one 8-bit counter interrupt ?e on-chip watchdog timer (wdt) ?e 99.9 h single instruction cycle commands ?e three action modes in crystal mode (main clock can be programmed to 3.58m or 14.3m hz) mode cpu status main clock 32.768khz clock status sleep mode turn off turn off turn off green mode turn on turn off turn on normal mode turn on turn on turn on ?e 2 level normal mode frequency: 3.58m and 14.3mhz. ?e input port interrupt function ?e dual clocks operation (internal pll main clock , external 32.768khz) operating frequency mode ?e crystal mode (xin,xout pin connect external crystal and capacitance) ?e eric mode (erci pin connect resister to vdd) ?e irc mode pwm ?e dual pwm (pulse width modulation) with 10-bit resolution ?e programmable period (or baud rate) ?e programmable duty cycle adc operating : 2.5v ?? 5.5v converter rate 74.6k 37.4k 18.7k 9.3k operating voltage(min) 3.5v 3.0v 2.5v 2.5v 8 channel 10-bit successive approximation a/d converter internal (vdd) reference voltage por power-on reset package EM78P5840m ? 18 pin sop, em78p5841m ? 20 pin sop, em78p5842m ? 24 pin sop EM78P5840p ? 18 pin pdip, em78p5841p ? 20 pin pdip, em78p5842p ? 24 pin pdip
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 4 2004/11/10 v2.6 iii. application general products application. iv. pin configuration (a) (b) (c) fig.1: EM78P5840 series pin assignment. (a): EM78P5840m, EM78P5840p (b): em78p5841m, em78p5841p (c): em78p5842m, em78p5842p p96 p95 cin/p94 ad7/p92 ad2/p91 ad1/p90 ad8/p93 /p70/int0 avss ad3/p62 ad6/p65 ad5/p64 ad4/p63 xin/p61 xout/p60 /reset/p71/int1 int3/p73 avdd 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 pllc/eric p96 p95 cin/p94 ad7/p92 ad2/p91 ad1/p90 ad8/p93 avss ad3/p62 ad6/p65 ad5/p64 ad4/p63 int3/p73 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 avdd pwm2/pc2 pwm1/pc1 19 20 /p70/int0 xin/p61 xout/p60 /reset/p71/int1 pllc/eric p95 cin/p94 ad7/p92 ad2/p91 ad1/p90 ad8/p93 avss ad3/p62 ad6/p65 ad5/p64 ad4/p63 int3/p73 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 avdd pwm2/pc2 pwm1/pc1 19 20 p96 22 21 23 24 p74 p75 p76 p97 /p70/int0 xin/p61 xout/p60 /reset/p71/int1 pllc/eric
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 5 2004/11/10 v2.6 v. functional block diagram timing control timer tcc counter1 counter2 wdt rom data ram control register i/o port cpu pwm 10-bit a/d fig.2a block diagram xin pllc oscillator timing control r1(tcc) prescaler wdt timer general ram r4 interrupt control instruction decoder instruction register rom r3 r5 acc alu stack data & control bus xout r2 control sleep and wakeup on i/o port pwm 10-bit a/d p62~p66 ioc6 r6 port6 p70 p73~p76 ioc7 r7 port7 p90~p97 ioc9 r9 port9 pc1~pc2 iocc rc portc p60~p61 p71 fig.2b block diagram
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 6 2004/11/10 v2.6 vi. pin descriptions pin i/o description power avdd power power avss power ground clock xin i input pin for 32.768 khz oscillator xout o output pin for 32.768 khz oscillator pllc i phase loop lock capacitor, connect a capacitor 0.047u to 0.1u to the ground. osc i eric mode clock signal input. this pin is shared with pllc. cin i counter1 external clk input. this pin is shared with p94. note the frequency of the input clk must less than 1m hz. 10-bit 8 channel a/d ad1 i (p90) adc input channel 1. shared with port90 ad2 i (p91) adc input channel 2. shared with port91 ad3 i (p62) adc input channel 3. shared with port62 ad4 i (p63) adc input channel 4. shared with port63 ad5 i (p64) adc input channel 5. shared with port64 ad6 i (p65) adc input channel 6. shared with port65 ad7 i (p92) adc input channel 7. shared with port92 ad8 i (p93) adc input channel 8. shared with port93 pwm pwm1 o pulse width modulation output this pin shared with portc1 pwm2 o pulse width modulation output this pin shared with portc2 io p60 ~ p61 i/o port60,1 can be input or output port each bit.. these two pins can be used on eric and irc modes. p62 ~p65 i/o port6 can be input or output port each bit. p70 i/o port70 can be input or output port each bit. p71 i port71 is input only. p73~p76 i/o port7 can be input or output port each bit. p90 ~ p97 i/o port9 can be input or output port each bit. pc1 ~ pc2 i/o portc can be input or output port each bit. int0 (port70) interrupt sources. once port70 has a falling edge or rising edge signal (controlled by cont register), it will generate a interruption. int1 (port71) interrupt sources which has the same interrupt flag. any pin from port71 has a falling edge signal, it will generate a interruption. int3 port73 interrupt sources which has the same interrupt flag. any pin from port73 has a falling edge signal, it will generate a interruption. /reset i low reset
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 7 2004/11/10 v2.6 vii. functional descriptions vii.1 operational registers register configuration r page registers addr r page0 r page1 r page2 r page3 00 indirect addressing 01 tcc 02 pc 03 page, status 04 ram bank, rsr 05 program rom page pwm control 06 port6 i/o data duty of pwm1 07 port7 i/o data adc msb output data pwm1 control duty of pwm1 08 period of pwm1 09 port9 i/o data duty of pwm2 0a pll, main clock, wdte pwm2 control duty of pwm2 0b adc output data buffer period of pwm2 0c portc i/o data counter1 data 0d 0e interrupt flag 0f interrupt flag 10 : 1f 16 bytes common registers 20 bank0 bank1 bank2 bank3 : common registers 3f (32x8 for each bank) *address 00~0f with page0~page3 are special registers. address 10~1f are global with general purpose memory. by setting mov instruction, mcu can read or write these regist er directly and ram bank select bits (rb1, rb0 in r4 page0) will be ignored. address 20~ 3f are general purpose ram too, but user must indicate the bank number before access data.
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 8 2004/11/10 v2.6 ioc page registers addr ioc page0 ioc page1 00 01 02 03 04 05 06 port6 i/o control port6 switches 07 port7 i/o control port7 pull high 08 09 port9 i/o control 0a 0b adc control 0c 0d clock source (cn1) prescaler(cn1) 0e interrupt mask 0f interrupt mask 10 : 1f 20 : 3f * ioc register are special registers. user can use instruction ?iow? to write data or ?ior? to read data. vii.2 operational regist er detail description r0 (indirect addressing register) r0 is not a physically implemented register. it is used as indirect addressing pointer. any instruction using r0 as register actually accesses data pointed by the ram select register (r4). example: mov a, @0x20 ;store a address at r4 for indirect addressing mov 0x04, a mov a, @0xaa ;write data 0xaa to r20 at bank0 through r0 mov 0x00, a r1 (tcc) tcc data buffer. increased by 16.384khz or by the instruction cycle clock (controlled by cont register). written and read by the program as any other register. r2 (program counter) the structure is depicted in fig.3. generates 4k 13 external rom addresses to the relative programming instruction codes. "jmp" instruction allows the direct loading of the low 10 program counter bits. "call" instruction loads the low 10 bits of the pc, pc+1, and then push into the stack. "ret'' ("retl k", "reti") instruction loads the program counter with th e contents at the top of stack. "mov r2, a" allows the loading of an address from the a register to the pc, and the ninth and tenth bits are cleared to "0''.
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 9 2004/11/10 v2.6 "add r2,a" allows a relative a ddress be added to the current pc, and contents of the ninth and tenth bits are cleared to "0''. "tbl" allows a relative address added to the current pc, and contents of the ninth and tenth bits don't change. the most significant bit (a10~a11) will be loaded with th e contents of bit ps0~ps1 in the status register (r5 page0) upon the execution of a "jmp'', "call'', "add r2, a'', or "mov r2, a'' instruction. if an interrupt is triggered, program rom will jump to address 0x08 at page0. the cpu will store acc, r3 status and r5 page automatically, and they will be restored after instruction reti. a11 a10 a9 a8 a7~a0 0 0 page0 00000~003ff 0 1 page1 00400~007ff 1 0 page2 00800~00bff stack1 stack2 stack5 stack4 stack3 stack6 stack8 stack7 call and interrupt ret retl reti acc,r3,r5(page) r5(page) store restore 1 1 page3 00c00~00fff fig.3 program counter organization r3 (status, page selection) (status flag, page selection bits) 7 6 5 4 3 2 1 0 rpage1 rpage0 iocpage t p z dc c r/w-0 r/w-0 r/w-0 r r r/w r/w r/w bit 0(c) : carry flag bit 1(dc) : auxiliary carry flag bit 2(z) : zero flag bit 3(p) : power down bit set to 1 during power on or by a "wdtc" co mmand and reset to 0 by a "slep" command. bit 4(t) : time-out bit set to 1 by the "slep" and "wdtc" command, or during power up and reset to 0 by wdt timeout. event t p remark wdt wake up from sleep mode 0 0 wdt time out (not sleep mode) 0 1 /reset wake up from sleep 1 0 power up 1 1 low pulse on /reset x x x : don't care bit 5(iocpage) : change ioc5 ~ ioce to another page please refer to fig.4 control register configuration for details. 0/1 ? ioc page0 / ioc page1 bit 6(rpage0 ~ rpage1) : change r5 ~ re to another page please refer to vii.1 operational regist ers for detail register configuration.
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 10 2004/11/10 v2.6 (rpage1,rpage0) r page # selected (0,0) r page 0 (0,1) r page 1 (1,0) r page 2 (1,1) r page 3 r4 (ram selection for co mmon registers r20 ~ r3f) (ram selection register) 7 6 5 4 3 2 1 0 rb1 rb0 rsr5 rsr4 rsr3 rsr2 rsr1 rsr0 r/w-0 r/w-0 r/w r/w r/w r/w r/w r/w bit 0 ~ bit 5 (rsr0 ~ rsr5) : indirect addressing for common registers r20 ~ r3f rsr bits are used to select up to 32 registers (r20 to r3f) in the indirect addressing mode. bit 6 ~ bit 7 (rb0 ~ rb1) : bank selection bits for common registers r20 ~ r3f these selection bits are used to determine which bank is activated among the 4 banks for 32 register (r20 to r3f).. please refer to vii.1 operational registers for details. r5 (program page selection, pwm control) page0 (port5 i/o data register, program page register) 7 6 5 4 3 2 1 0 x x x x 0 0 ps1 ps0 - - - - r/w-0 r/w-0 r/w-0 r/w-0 bit 0 ~ bit 1 (ps0 ~ ps1) : program page selection bits ps1 ps0 program memo ry page (address) 0 0 page 0 0 1 page 1 1 0 page 2 1 1 page 3 user can use page instruction to change page to maintain program page by user. bit2~bit3 : (undefined) these 2 bits must clea r to 0 or mcu will access wronging program code. bit4~bit7: (undefined) not allowed to use page1, page2 (unused registers) these two registers are not allowed to used. page3 (pwmcon) 7 6 5 4 3 2 1 0 pwm2e pwm1e t2en t1en t2p1 t2p0 t1p1 t1p0 r/w-0 r/w-0 r/w-0 r/ w-0 r/w-0 r/w-0 r/w-0 r/w-0 bit 0 ~ bit 1 ( t1p0 ~ t1p1 ): tmr1 clock prescale option bits. t1p1 t1p0 prescale 0 0 1:2(default) 0 1 1:8 1 0 1:32 1 1 1:64 bit 2 ~ bit 3 ( t2p0 ~ t2p1 ): tmr2 clock prescale option bits. t2p1 t2p0 prescale 0 0 1:2(default) 0 1 1:8
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 11 2004/11/10 v2.6 1 0 1:32 1 1 1:64 bit 4 (t1en): tmr1 enable bit 0 ? tmr1 is off (default value). 1 ? tmr1 is on. bit 5 (t2en): tmr2 enable bit 0 ? tmr2 is off (default value). 1 ? tmr2 is on. bit 6 (pwm1e): pwm1 enable bit 0 ? pwm1 is off (default value), and its related pin carries out the pc1 function; 1 ? pwm1 is on, and its related pin will be set to output automatically. bit 7 (pwm2e): pwm2 enable bit 0 ? pwm2 is off (default value), and its related pin carries out the pc2 function. 1 ? pwm2 is on, and its related pin will be set to output automatically. r6 (port6 i/o data, pwm control) page0 (port6 i/o data register) 7 6 5 4 3 2 1 0 x x p65 p64 p6 3 p62 p61 p60 - - r/w r/w r/w r/w r/w r/w bit0 ~ bit1 (p60 ~ p61): port60 and port61 can be used on irc and eric mode. in these two mode, port60 and port61 will defined to general purpose io. in cr ystal mode, port60 and port 61 are defined to crystal input (xin and xout) pins and these two bits are undefined. bit2 ~ bit6 (p62 ~ p65): 4-bit port6(2~5) i/o data register user can use ioc register to define input or output each bit. bit6 ~ bit7 : unused register. these bits are not allowed to use. page1, page2 : (undefined) not allowed to use these two registers are not allowed to use. page3 (dt1l: the least significant byte ( bit 7 ~ bit 0) of duty cycle of pwm1) 7 6 5 4 3 2 1 0 pwm1[7] pwm1[6] pwm1[5] pwm1[4] pwm1[3] pwm1[2] pwm1[1] pwm1[0] r/w-0 r/w-0 r/w-0 r/ w-0 r/w-0 r/w-0 r/w-0 r/w-0 a specified value keeps the output of pwm1 to stay at high until the value matches with tmr1.
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 12 2004/11/10 v2.6 r7 (port7 i/o data, adc, duty cycle of pwm ) page0 (port7 i/o data register) 7 6 5 4 3 2 1 0 x p76 p75 p74 p73 x p71 p70 - r/w r/w r/w r/w - r r/w bit0 (p70): port70 is a multi-function pin. in crystal mode, by setting p70s in code option, port70 will be general purpose io or pllc. please do not enable pll function if port70 defined to io. in irc or eric mode, this pin will defined to port70 and p70s will be ignored. p70 is port70 i/o data register and user can use ioc register to define input or out put each bit. bit1 (p71): port71 is shared with /reset pin. by se tting p71s in code option, port71 will defined to input pin or /reset pin. this register is a read only bit. p71 dose not support internal pull high function. if user want to use p71 interrupt, external pull high is necessary. bit3 ~ bit6 (p73 ~ p76): 4 - bit port7 i/o data register user can use ioc register to define input or output each bit. page1 (adc resolution selection bit and adc msb output data) 7 6 5 4 3 2 1 0 x x ad9 ad8 x adres 0 0 - - r r - r/w-0 r-0 r-0 bit 0~bit 1: undefined register. these two bits are not allowed to use. these bits must clear to 0. bit 2(adres) : resolution selection for adc 0 ? adc is 8-bit resolution when 8-bit resolution is selected, the most significant(msb) 8-bit data output of the internal 10-bit adc will be mapping to rb page1 so r7 page1 bit 4 ~5 will be of no use. 1 ? adc is 10-bit resolution when 10-bit resolution is selected, 10-bit data output of the internal 10-bit adc will be exactly mapping to rb page1 and r7 page1 bit 4 ~5. bit 3 : (undefined) not allowed to use bit 4 ~ bit 5(ad8 ~ ad9) : the most significant 2 bit of 10-bit adc conversion output data combine there two bits and rb page1 as complete 10-bit adc conversion output data. bit 6 ~ bit 7 : (undefined) not allowed to use page2 : (undefined) not allowed to use page3 (dt1h: the most significant byte ( bit 1 ~ bit 0 ) of duty cycle of pwm) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 pwm1[9] pwm1[8] r-0 r-0 r-0 r-0 r-0 r-0 r/w-0 r/w-0 bit 0 ~ bit 1 (pwm1[8] ~ pwm1[9]): the most significant two bits of pwm1 duty cycle bit 2 ~ bit 7 : unused. r8 (data ram address, pwm1 period) page0: (undefined) not allowed to use page1: (undefined) not allowed to use page2: (undefined) not allowed to use page3 (prd1: period of pwm) 7 6 5 4 3 2 1 0 prd1[7] prd1[6] prd1[5] prd1[4] prd1[3] prd1[2] prd1[1] prd1[0] r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 the content of this register is a period (time base) of pwm1. the frequency of pwm1 is the reverse of the period.
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 13 2004/11/10 v2.6 r9 (port9 i/o data) page0 (port9 i/o data register) 7 6 5 4 3 2 1 0 p97 p96 p95 p94 p93 p92 p91 p90 r/w r/w r/w r/w r/w r/w r/w r/w bit 0 ~ bit 7 (p90 ~ p97) : 8-bit port9(0~7) i/o data register user can use ioc register to define input or output each bit. page1: (undefined) not allowed to use page2: (undefined) not allowed to us page3 (dt2l: the least significant byte ( bit 7 ~ bit 0 ) of duty cycle of pwm2) 7 6 5 4 3 2 1 0 pwm2[7] pwm2[6] pwm2[5] pwm2[4] pwm2[3] pwm2[2] pwm2[1] pwm2[0] r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 a specified value keeps the output of pwm2 to stay at high until the value matches with tmr2. ra (pll, main clock selection, watchdog timer) page0 (pll enable bit, main clock selection bits, watchdog timer enable bit) 7 6 5 4 3 2 1 0 0 pllen clk2 clk1 clk0 x x wdten r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 - - r/w-0 bit 0(wdten) : watch dog control bit. 0/1 ? disable/enable user can use wdtc instruction to clear watch dog counter. the watchdog timer is a free running on-chip rc oscillator. the wdt will keep on running even after the osc illator driver has been turned off (i.e. in sleep mode). during normal operation or sleep mode, a wdt time-out (if enabled) will cause the device to reset. the wdt can be enabled or disabled at any time during the green mode or normal mode by software programming. without presacler, the wdt time-out period is approximately 18 ms. bit 1~bit 2 : unused bit 3 ~ bit 5 (clk0 ~ clk2) : main clock selection b its on crystal mode. these th ree bits are unused on irc and eric mode. in crystal mode: user can choose different frequency of main clock by clk1 and clk2. all the clock selection is list below. pllen clk2 clk1 clk0 sub clock main clock cpu clock 1 0 0 0 32.768khz 3.582mhz 3.582mhz (normal mode) 1 0 0 1 32.768khz 3.582mhz 3.582mhz (normal mode) 1 0 1 0 32.768khz 3.582mhz 3.582mhz (normal mode) 1 0 1 1 32.768khz 3.582mhz 3.582mhz (normal mode) 1 1 0 0 32.768khz 14.3mhz 14.3mhz (normal mode) 1 1 0 1 32.768khz 14.3mhz 14.3mhz (normal mode) 1 1 1 0 32.768khz 14.3mhz 14.3mhz (normal mode) 1 1 1 1 32.768khz 14.3mhz 14.3mhz (normal mode) 0 don?t care don?t care don?t care 32.768khz don?t care 32.768khz (green mode) bit 6(pllen) : pll's power control bit which is cpu mode control register. this bit is only used in crystal mode. in rc mode, this bit will be ignored. 0/1 ? disable pll/enable pll
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 14 2004/11/10 v2.6 if enable pll, cpu will operate at normal mode (hig h frequency). otherwise, it will run at green mode (low frequency, 32768 hz). sub-clock 32.768khz switch 0 1 system clock pll circuit 3.58mhz, 14.3mhz enpll clk2 ~ clk0 fig.4 the relation between 32.768khz and pll bit 7: unused register. always keep this bit to 0 or some un-expect error will happen! next table show the status after wake-up and the wake-up sources list wakeup signal sleep mode ra(7,6)=(0,0) + slep tcc time out iocf bit0=1 no function counter1 time out iocf bit1=1 no function wdt time out reset and jump to address 0 port7 (0,1,3) reset and jump to address 0 port70 's wakeup function is controlled by iocf bit 3. it's falling edge or rising edge trigger (controlled by cont register bit7). port71 's wakeup function is controlled by iocf bit 4. it?s falling edge trigger. port73 's wakeup function is controlled by iocf bit 5. it is falling edge trigger. page1,2 : (undefined) not allowed to use page3 (dt2h: the most significant byte ( bit 1 ~ bit 0 ) of duty cycle of pwm2) 7 6 5 4 3 2 1 0 x x x x x x pwm2[9] pwm2[8] - - - - - - r/w-0 r/w-0 bit 0 ~ bit 1 (pwm2[8] ~ pwm2[9]): the most significant byte of pwm1 duty cycle a specified value keeps the pwm1 output to stay at high until the value matches with tmr1. bit 2 ~ bit 7 : (undefined) not allowed to use
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 15 2004/11/10 v2.6 rb (adc input data buffer) page0 : (undefined) not allowed to use page1 (adc output data register) 7 6 5 4 3 2 1 0 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r r r r r r r r bit 0 ~ bit 7 (ad0 ~ ad7) : the last significant 8 bit of 10-bit or whole of 8 bit resolution adc conversion output data. combine there 8 bits and r7 page1 bit4~5 as complete 10-bit adc conversion output data in 10 bit resolution mode. page 2 (undefined) not allowed to use page3 (prd2: period of pwm2) 7 6 5 4 3 2 1 0 prd2[7] prd2[6] prd2[5] prd2[4] prd2[3] prd2[2] prd2[1] prd2[0] r/w-0 r/w-0 r/w-0 r/w-0 r/ w-0 r/w-0 r/w-0 r/w-0 the content of this register is a period (time base) of pwm2. the frequency of pwm2 is the reverse of the period. rc (portc i/o data, counter1 data) page0 (port9 i/o data register) 7 6 5 4 3 2 1 0 x x x x x pc2 pc1 x - - - - - r/w r/w - bit 1 ~ bit 2 (pc1 ~ pc2) : portc1,portc2 i/o data register user can use ioc register to define input or output each bit. bit 0; bit 3~bit 7: (undefined) not allowed to use.(these bits are not sure to 0 or 1 ) page1 (counter1 data register) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 cn17 cn16 cn15 cn14 cn13 cn12 cn11 cn10 r/w-0 r/w-0 r/w-0 r/w-0 r/ w-0 r/w-0 r/w-0 r/w-0 bit 0 ~ bit 7 (cn10 ~ cn17) : counter1's buffer that user can read and write. counter1 is a 8-bit up-counter with 8-bit prescaler that user can use rc page1 to preset and read the counter.(write ? preset) after a interruption , it will reload the preset value. example for writing : mov 0x0c, a ; write the data at accumulator to counter1 (preset) example for reading : mov a, 0x0c ; read the da ta at counter1 to accumulator page2,3 (undefined) not allowed to use. rd (undefined register) page0 (unused) 7 6 5 4 3 2 1 0 x 0 0 0 x 0 0 0 - r/w-0 r/w-0 r/w-0 - r/w r/w r/w bit 0 ~bit 2 : these three bits must clear to 0 or mcu power consumption will increase. bit 3 , bit 7 : (undefined) not allowed to use bit4 ~ bit6 : these 3 bits are unused in mask/otp em785840, but they are us ed for ice5830. about the definition of these 3 bits, please refer to appendix ii. in ice5830, please clear bit4, bit5 and bit6 to 0. page1,2,3 (undefined) not allowed to use.
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 16 2004/11/10 v2.6 re (interrupt flag) page0 (interrupt flag) 7 6 5 4 3 2 1 0 pwm2 0 adi pwm1 0 0 0 0 r/w-0 r/w-0 r/w-0 r/w-0 r/ w-0 r/w-0 r/w-0 r/w-0 bit0 ~ bit3, bit6: these four bits must clear to 0 or unable to expect error will occur . bit 4(pwm1) : pwm1 one period reach interrupt flag. bit 5 (adi) : adc interrupt flag after a sampling bit 7 (pwm2) : pwm2 (pulse width modulation channel 2) interrupt flag set when a selected period is reached, reset by software. page2,3 (undefined) not allowed to use. rf (interrupt status) (interrupt status register) 7 6 5 4 3 2 1 0 int3 0 0 int1 int0 0 cnt1 tcif r/w-0 r/w-x r/w-x r/w-0 r/w-0 r/w-x r/w-0 r/w-0 "1" means interrupt request, "0" means non-interrupt bit 0(tcif) : tcc timer overflow interrupt flag set when tcc timer overflows. bit 1(cnt1) : counter1 timer overflow interrupt flag set when counter1 timer overflows. bit 2,5,6: unused (these bits are not sure to 0 or 1. when programmer determine what interrupt occur in subroutine, be care to note these bits) bit 3(int0): by setting port70 to general io, int0 will define to port70 pin?s interrupt flag. if port70 has a falling edge/rising edge (controlled by cont register ) trigger signal, cpu will set this bit. if setting the pin to pllc or osci, port70 interrupt will un-exist and int0 register will be ignored. bit 4(int1): by setting port71 to general io, int1 will define to port71 pin?s interrupt flag. external pull high circuit is needed for port71 interrupt operatio n. if port71 has a falling edge trigger signal, cpu will set this bit. if setting the pin to /reset, port71 interrupt will un-exist an d int1 register will be ignored. bit 7(int3): external port73 pin inte rrupt flag. if port73 has a falling edge trigger signal, cpu will set this bit. iocf is the interrupt mask register. user can read and clear. trigger edge as the table signal trigger tcc time out counter1 time out int0 falling rising edge int1 falling edge int3 falling edge r10~r3f (general purpose register) r10~r3f (banks 0 ~ 3) : all are general purpose registers.
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 17 2004/11/10 v2.6 vii.3 special purpose registers a (accumulator) internal data transfer, or instruction operand holding it's not an addressable register. cont (control register) 7 6 5 4 3 2 1 0 p70eg int ts retb k pab psr2 psr1 psr0 r/w-1 r/w-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 bit 0 ~ bit 2 (psr0 ~ psr2) : tcc/wdt prescaler bits psr2 psr1 psr0 tcc rate wdt rate 0 0 0 1:2 1:1 0 0 1 1:4 1:2 0 1 0 1:8 1:4 0 1 1 1:16 1:8 1 0 0 1:32 1:16 1 0 1 1:64 1:32 1 1 0 1:128 1:64 1 1 1 1:256 1:128 bit 3(pab) : prescal er assignment bit 0/1 ? tcc/wdt bit 4(retbk) : return value backup control for interrupt routine 0/1 ? disable/enable when this bit is set to 1, the cpu will store acc,r3 st atus and r5 page automatically after an interrupt is triggered. and it will be restored after instruction reti. when this bit is set to 0, the user need to store acc, r3 and r5 page in user program. bit 5(ts) : tcc signal source 0 ? internal instruction cycle clock 1 ? irc output bit 6 (int) : int enable flag 0 ? interrupt masked by disi or hardware interrupt 1 ? interrupt enabled by eni/reti instructions bit 7 (p70eg): if switch port70 to int0 input, p70eg can select the interrupt toggle type. 0 ? p70 's interruption source is a rising edge signal and falling edge signal. 1 ? p70 's interruption source is a falling edge signal. cont register is readable (contr) and writable (contw). tcc and wdt : there is an 8-bit counter available as prescaler for the tcc or wdt. th e prescaler is available for the tcc only or wdt only at the same time. an 8 bit counter is available for tcc or wdt determined by the status of the bit 3 (pab) of the cont register. see the prescaler ratio in cont register. fig.5 depicts the circuit diagram of tcc/wdt.
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 18 2004/11/10 v2.6 irc1 (32k) pll output irc2 oscillator erc oscillator oscm1,0 fig.5 block diagram of tcc wdt ioc5 (unused) page0 (unused) 7 6 5 4 3 2 1 0 0 0 0 - - - - - r/w r/w r/w bit0~4 : (undefined) not allowed to use bit5~bit7(unused) : these three bits must clea r to 0 or mcu power consumption will increase. the default value in these 3 bits are ?1?. please clear them to ?0? when init mcu. page1 (undefined) not allowed to use. (this page is not sure to 0 or 1 ) ioc6 (port6 i/o control, p6* pins switch control) page0 (port6 i/o control register) 7 6 5 4 3 2 1 0 0 0 ioc65 ioc64 ioc63 ioc62 ioc61 ioc60 - - r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 bit0~bit1: in crystal mode, these two bits are unused re gisters. in irc or eric mode, port60 and port61 are i/o direction control register. bit 2 ~ bit 5 (ioc62 ~ ioc65) : port6(2~5) i/o direction control register 0 ? put the relative i/o pin as output 1 ? put the relative i/o pin into high impedance bit6~bit7 (unused): these2 bits must clear to 0 or mcu power consumption will increase. the default value in these 2 bits are ?1?. please clear them to ?0? when init mcu.
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 19 2004/11/10 v2.6 page1 (p6* pins switch control register) 7 6 5 4 3 2 1 0 x 0 p65s p64s p63s p62s p91s p90s - r/w-0 r/w-0 r/w-0 r/ w-0 r/w-0 r/w-0 r/w-0 adc channel 1 and channel 2 are shared with port90 and port91. bit 0(p90s) : select normal i/o port90 pin or channel 1 input ad1 pin of adc 0 ? p90 (i/o port90) pin is selected 1 ? ad1 (channel 1 input of adc) pin is selected bit 1(p91s) : select normal i/o port91 pin or channel 2 input ad2 pin of adc 0 ? p91 (i/o port91) pin is selected 1 ? ad2 (channel 2 input of adc) pin is selected bit 2(p62s) : select normal i/o port62 pin or channel 3 input ad3 pin of adc 0 ? p62 (i/o port62) pin is selected 1 ? ad3 (channel 3 input of adc) pin is selected bit 3(p63s) : select normal i/o port63 pin or channel 4 input ad4 pin of adc 0 ? p63 (i/o port63) pin is selected 1 ? ad4 (channel 4 input of adc) pin is selected bit 4(p64s) : select normal i/o port64 pin or channel 5 input ad5 pin of adc 0 ? p64 (i/o port64) pin is selected 1 ? ad5 (channel 5 input of adc) pin is selected bit 5(p65s) : select normal i/o port65 pin or channel 6 input ad6 pin of adc 0 ? p65 (i/o port65) pin is selected 1 ? ad5 (channel 6 input of adc) pin is selected bit 6: unused register. please clear this bit to 0 or adc result will wronging. bit 7: unused register. this bit is nor allowed to use. ioc7 (port7 i/o control, port7 pull high control) page0 (port7 i/o control register) 7 6 5 4 3 2 1 0 x ioc76 ioc75 ioc74 ioc73 x x ioc70 - r/w-1 r/w-1 r/w-1 r/w-1 - - r/w-1 bit0(ioc70): port70 pin will defined to general purp ose io, pllc or osc by setting code option. in irc mode or crystal mode(only at code option p70s =0 ), port70 pin will be a general purpose io. ioc70 is port70 pin?s i/o direction control register. 0 ? put the relative i/o pin as output 1 ? put the relative i/o pin into high impedance bit1 (unused) : this bit is unused registers. by setti ng p71s = 1 in code option, port71 pin will be a input only pin. bit2; bit7 (unused) : these 2 bits must clea r to 0 or mcu power co nsumption will increase. the default value in these 3 bits are ?1 ?. please clear them to ?0? when init mcu. bit3~bit6 (ioc73~ioc76) : port7 i/o direction control register 0 ? put the relative i/o pin as output 1 ? put the relative i/o pin into high impedance page1 (port7 pull high control register) 7 6 5 4 3 2 1 0 x ph76 ph75 ph74 ph73 x x ph70 - r/w-0 r/w-0 r/w-0 r/w-0 - - r/w-0 bit0: port70 pull high control register. this b it only exist on setting port 70 general purpose io. 0 ? disable pull high function. 1 ? enable pull high function bit1, bit7 (unused): these2 b its must clear to 0 or mcu power consumption will increase. bit3~bit6 : port7 pull high control register
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 20 2004/11/10 v2.6 0 ? disable pull high function. 1 ? enable pull high function ioc8 (unused), not allowed to use ioc9 (port9 i/o control, port9 switches) page0 (port9 i/o control register) 7 6 5 4 3 2 1 0 ioc97 ioc96 ioc95 ioc94 ioc93 ioc92 ioc91 ioc90 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 bit 0 ~ bit 7 (ioc90 ~ ioc97) : port9(0~7) i/o direction control register 0 ? put the relative i/o pin as output 1 ? put the relative i/o pin into high impedance page1 (unused) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 **these 8 bits must clear to 0 or port9 input or output function will wronging ioca (unused) page0 (undefined) not allowed to use page1 unused 7 6 5 4 3 2 1 0 x 0 x x 0 x ad8s ad7s - r/w - - r/w - r/w-0 r/w-0 bit 0(ad7s) : select normal i/o port92 pin or channel 7 input ad7 pin of adc 0 ? p92 (i/o port92) pin is selected 1 ? ad7 (channel 7 input of adc) pin is selected bit 1(ad8s) : select normal i/o port93 pin or channel 8 input ad8 pin of adc 0 ? p93 (i/o port93) pin is selected 1 ? ad8 (channel 8 input of adc) pin is selected bit3 , bit6 (unused) : these 2 bits must clea r to 0 or mcu power consumption will increase. bit2 ~ bit7 are undefined register, they are not allowed to use.
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 21 2004/11/10 v2.6 iocb (adc control) page0 (unused) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ** this page must clear to 0 or mcu power consumption will increase. the default value in these 8 bits are ?1?. please clear them to ?0? when init mcu. page1 (adc control bits) 7 6 5 4 3 2 1 0 in2 in1 in0 adclk1 adclk0 adpwr 0 adst r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bit 0(adst) : ad converter start to sample by setting to ?1?, the ad will start to sample data. th is bit will be cleared by hardware automatically after a sampling. bit 1 : (undefined) not allowed to use. this bit must clear to 0. bit 2(adpwr) : ad converter power control, 1/0 ? enable/disable. bit 3 ~ bit 4 (adclk0 ~ adclk1) : ad circuit ?s sampling clock source. for crystal mode: adclk1 adclk0 sampling rate operation voltage 0 0 74.6k >=3.5v 0 1 37.4k >=3.0v 1 0 18.7k >=2.5v 1 1 9.3k >=2.5v for irc or eric mode, ad converter rate will change by oscillator. the formula for input frequency and ad converter rate is: ad converter rate = oscillator / 4 / (2^adclk)/12 for example, if input clk = 4m hz: adclk1 adclk0 sampling rate operation voltage 0 0 83.3k >=3.5v 0 1 41.7k >=3.0v 1 0 20.8k >=2.5v 1 1 10.4k >=2.5v * please avoid ad converter rate over 50 k hz, it maybe decrease adc?s resolution. this is a cmos multi-channel 10-bit su ccessive approximation a/d converter. features 74.6khz maximum conversion speed (crystal mode) at 5v. adjusted full scale input internal (vdd) reference voltage 8 analog inputs multiplexed into one a/d converter power down mode for power saving a/d conversion complete interrupt interrupt register, a/d control and status register, and a/d data register
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 22 2004/11/10 v2.6 fig.6 adc voltage control logic bit 5 ~ bit 7(in0~ in2) : input ch annel selection of ad converter these two bits can choose one of three ad input. in2 in1 in0 input pin 0 0 0 ad1 p90 0 0 1 ad2 p91 0 1 0 ad3 p62 0 1 1 ad4 p63 1 0 0 ad5 p64 1 0 1 ad6 p65 1 1 0 ad7 p92 1 1 1 ad8 p93 *before switch to the ad channel, please set the corresponding pin as ad input. iocc (portc i/o control, adc control) page0 (portc i/o control) 7 6 5 4 3 2 1 0 0 0 0 0 0 iocc2 iocc1 0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 bit 1 ~ bit 2 (iocc1 ~ iocc2) : portc( 1~2) i/o direction control register 0 ? put the relative i/o pin as output 1 ? put the relative i/o pin into high impedance ** bit0 , bit3 ~ bit7 must clear to 0 or mcu power consum ption will increase. the default value in these 6 un-define bits are ?1?. please clear them to ?0? when init mcu. page1 (port switch) 7 6 5 4 3 2 1 0 - - - - - - - 1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w/0 bit 0: always set this bit to ?1? otherw ise partial adc function cannot be used) bit 1 ~ bit 7: (undefined) not allowed to use programmable divider 1/mx divider nx 10-bit adc adclk1~adclk0 fs adc output pll enpll clk2 ~ clk0 fpll fadc
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 23 2004/11/10 v2.6 iocd (tone1 control, cloc k source, prescaler of cn1) page0 (reserved) page1 (clock source and prescaler for counter1) 7 6 5 4 3 2 1 0 cnti/es x x x cnt1s c1_psc 2 c1_psc1 c1_psc0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bit 0 ~ bit 2 (c1_psc0 ~ c1_psc2) : counter1 prescaler ratio c1_psc2 c1_psc1 c1_psc0 counter1 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 bit 3(cnt1s) : counter1 clock sour ce. this bit will un-effect on rc mode (rc mode?s clk is always equal to oscillator frequency). 0/1 ? 16.384khz / system clock. prescaler fosc fpll 8-bit counter trl reload timer en psr2..psr0 cnt1s timer interrupt timer wake up overflow oscm1,0 irc2 p94 cnti/es erc fig 7: timer clk source diagram bit4 ~ bit6: unused register. these three bits are not allowed to use. bit7 (cnti/es):counter source select. cnti/es = 0 ? timer counter clk come from system clk or crystal output and p94 is defined to general propose io. chti/es = 1 ? p94 is defined to input and timer counter ?s clk will come from p94?s falling edge. ioce (interrupt mask,) page0 (interrupt mask) 7 6 5 4 3 2 1 0 pwm2 0 adi pwm1 x x x x r/w-0 r/w-0 r/w-0 r/w-0 - - - - bit 0 ~ bit 3 : unused bit 4(pwm1) : pwm1 one period reach interrupt mask. bit 5 (adi) : adc conversion complete interrupt mask 0/1 ? disable/enable interrupt there are four registers for a/d converter. use one bit of interrupt control register (ioce page0 bit5) for
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 24 2004/11/10 v2.6 a/d conversion complete interrupt. the status and control register of a/d (iocb page1 and re page0 bit5) responses the a/d conversion status or takes control on a/d. the a/d data register (rb page1) stores a/d conversion result. adi bit in ioce page0 register is end of a/d co nversion complete interrupt enable/disable. it enables/disables adi flag in re register when a/d conv ersion is complete. adi flag indicates the end of an a/d conversion. the a/d converter sets the interrupt fl ag, adi in re page0 register when a conversion is complete. the interrupt can be disabled by setting adi bit in ioce page0 bit5 to ?0?. the a/d converter has eight analog input channels ad1~ad8 multiplexed into one sample and hold to a/d module. reference voltage can be driven from internal power. the a/d converter itself is of an 10-bit successive approximation type and produces lost significant 8-bit result in the rb page1 and most significant 2 bit to r7 page1 bit4, bit5. a conversion is initiated by setting a control bit adst in iocb page1 bit0. prior to conversion, the appropriate channe l must be selected by setting in0~in2 bits in re register and allowed for enough time to sample data . every conversion data of a/d need 12-clock cycle time. the minimum conversion time required is 13 us (73k sample rate). adst bit in iocb page1 bit0 must be set to begin a conversion. it will be automatically reset in hardware when conversion is complete. at the end of conversion, the start bit is cleared and the a/d interrupt is activated if adi in ioce page0 b it5 = 1. adi will be set when conversion is complete. it can be reset in software. if adi = 0 in ioce page0 bit5, when a/d start conversion by setting adst(iocb page1 bit0) = 1 then a/d will continue conversion without stop and hardware won?t reset adst bit. in this condition, adi is deactived. after adi in ioce page0 bit5 is set, adi in re page0 bit5 will activate again. to minimum operating current , all biasing circuits in the a/d module that consume dc current are power down when adpwr bit in iocb page1 bit2 register is a ?0?. when adpwr bit is a ?1?, a/d converter module is operating. fig.8 a/d converter timing bit 6: undefined register. please clear this bit to 0. bit 7 (pwm2) : pwm2 interrupt enable bit 0/1 ? disable/enable interrupt 1 2 3 4 5 6 7 8 9 10 start sample adi(ioce page0 bit5 ) =1 adi(re page0 bit 5) data clear by software
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 25 2004/11/10 v2.6 iocf (interrupt mask) (interrupt mask register) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 int3 x x int1 int0 x cnt1 tcif r/w-0 - - r/w-0 r/w-0 - r/w-0 r/w-0 bit 0~1; 3~4 ; bit 7 : interrupt enable bit 0 ? disable interrupt 1 ? enable interrupt bit 2, 5~6 : (remain these values to ?0?othw ise it will generate unpredicted interrupts) the status after interrupt and the interrupt sources list as the table below. interrupt signal sleep mode green mode normal mode eni reset and jump to address 0 interrupt (jump to address 8 at page0) interrupt (jump to address 8 at page0) tcc time out iocf bit0=1 and "eni" disi no function no function no function counter1 time out iocf bit1=1 and "eni" no function interrupt (jump to address 8 at page0) interrupt (jump to address 8 at page0) port70 only at irc mode or crystal mode (at p70s = 0) reset and jump to address 0 interrupt (jump to address 8 at page0) interrupt (jump to address 8 at page0) port71 only at p71s = 0 reset and jump to address 0 interrupt (jump to address 8 at page0) interrupt (jump to address 8 at page0) port73 iocf bit3 bit7 =1 and "eni" reset and jump to address 0 interrupt (jump to address 8 at page0) interrupt (jump to address 8 at page0) adi ioce bit5 = 1 and ?eni no function no function interrupt (jump to address 8 at page0) pwm1 ioce bit4 = 1 and ?eni no function interrupt (jump to address 8 at page0) interrupt (jump to address 8 at page0) port70 's interrupt function is controlled by iocf bit 3. it's falling edge or rising edge trigger (controlled by cont register bit7). port71 's interrupt function is controlled by iocf bit 4. it?s falling edge trigger. port73 's interrupt function is controlled by iocf bit 7. they are falling edge trigger. adi interrupt source function is controlled by re page 0 bit 5. it is rising edge trigger after adc sample complete.
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 26 2004/11/10 v2.6 vii.4 i/o port the i/o registers are bi-directional tri-state i/o ports. the i/o ports can be defined as "input" or "output" pins by the i/o control registers under program control. the i/o data registers and i/o control registers are both readable and writable. the i/o interface circuit is shown in fig.9. fig.9_1 the circuit of i/o port and i/o control register pin 120 ohm vdd vdd vdd pull high fig.9_2 the input/output circuit of em785840 input/output ports m u x 0 1 pdrd pdwr clk c l p r d q q clk c l p r d q q pcwr iod pcrd port
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 27 2004/11/10 v2.6 vii.5 reset the reset can be caused by (1) power on reset (2) wdt timeout. (if enabled and in green or normal mode) (3) /reset pin pull low (at p71s = 1). once the reset occurs, the following functions are performed. ? the oscillator is running, or will be started. ? the program counter (r2) is set to all "0". ? when power on, the upper 3 bits of r3 and the upper 2 bits of r4 are cleared. ? the watchdog timer and pres caler counter are cleared. ? the watchdog timer is disabled. vii.6 wake-up the controller provided sleep mode for power saving : sleep mode, ra(7) = 0 + "slep" instruction the controller will turn off all the cp u and crystal. other circuit with power control like key tone control or pll control (which has enable register), user has to turn it off by software. wake-up from sleep mode (1) wdt time out (2) external interrupt (3) /reset pull low all these cases will reset controller , and run the program at address zero. the status just like the power on reset. vii.7 interrupt rf is the interrupt status register which records the inte rrupt request in flag bit. iocf is the interrupt mask register. global interrupt is enabled by eni instruction and is disabled by disi instruction. when one of the interrupts (when enabled) generated, will cause the next instruction to be fetched from address 008h. once in the interrupt service routine, the source of the interrupt can be determined by polling the flag bits in the rf register. the interrupt flag bit must be clear ed in software before leaving the interrupt service routine and enabling interrupts to avoid recursive interrupts.
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 28 2004/11/10 v2.6 vii.8 instruction set instruction set has the following features: (1) every bit of any register can be set, cleared, or tested directly. (2) the i/o register can be regarded as general regist er. that is, the same instruction can operates on i/o register. the symbol "r" represents a register designator which specifies which one of the 64 registers (including operational registers and general purpose registers) is to be utilized by the instruction. bits 6 and 7 in r4 determine the selected register bank. "b'' represents a b it field designator which selects the number of the bit, located in the register "r'', affected by the operation. "k'' represents an 8 or 10-bit constant or literal value. instruction binary hex mnemonic operation status affected instruction cycle 0 0000 0000 0000 0000 nop no operation none 1 0 0000 0000 0001 0001 daa decimal adjust a c 1 0 0000 0000 0010 0002 contw a cont none 1 0 0000 0000 0011 0003 slep 0 wdt, stop oscillator t,p 1 0 0000 0000 0100 0004 wdtc 0 wdt t,p 1 0 0000 0000 rrrr 000r iow r a iocr none 1 0 0000 0001 0000 0010 eni enable interrupt none 1 0 0000 0001 0001 0011 disi disable interrupt none 1 0 0000 0001 0010 0012 ret [top of stack] pc none 2 0 0000 0001 0011 0013 reti [top of stack] pc enable interrupt none 2 0 0000 0001 0100 0014 contr cont a none 1 0 0000 0001 rrrr 001r ior r iocr a none 1 0 0000 0010 0000 0020 tbl r2+a r2 bits 9,10 do not clear z,c,dc 2 0 0000 01rr rrrr 00rr mov r,a a r none 1 0 0000 1000 0000 0080 clra 0 a z 1 0 0000 11rr rrrr 00rr clr r 0 r z 1 0 0001 00rr rrrr 01rr sub a,r r-a a z,c,dc 1 0 0001 01rr rrrr 01rr sub r,a r-a r z,c,dc 1 0 0001 10rr rrrr 01rr deca r r-1 a z 1 0 0001 11rr rrrr 01rr dec r r-1 r z 1 0 0010 00rr rrrr 02rr or a,r a r a z 1 0 0010 01rr rrrr 02rr or r,a a r r z 1 0 0010 10rr rrrr 02rr and a,r a & r a z 1 0 0010 11rr rrrr 02rr and r,a a & r r z 1 0 0011 00rr rrrr 03rr xor a,r a r a z 1 0 0011 01rr rrrr 03rr xor r,a a r r z 1 0 0011 10rr rrrr 03rr add a,r a + r a z,c,dc 1 0 0011 11rr rrrr 03rr add r,a a + r r z,c,dc 1 0 0100 00rr rrrr 04rr mov a,r r a z 1 0 0100 01rr rrrr 04rr mov r,r r r z 1 0 0100 10rr rrrr 04rr coma r /r a z 1 0 0100 11rr rrrr 04rr com r /r r z 1
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 29 2004/11/10 v2.6 0 0101 00rr rrrr 05rr inca r r+1 a z 1 0 0101 01rr rrrr 05rr inc r r+1 r z 1 0 0101 10rr rrrr 05rr djza r r-1 a, skip if zero none 2 if skip 0 0101 11rr rrrr 05rr djz r r-1 r, skip if zero none 2 if skip 0 0110 00rr rrrr 06rr rrca r r(n) a(n-1) r(0) c, c a(7) c 1 0 0110 01rr rrrr 06rr rrc r r(n) r(n-1) r(0) c, c r(7) c 1 0 0110 10rr rrrr 06rr rlca r r(n) a(n+1) r(7) c, c a(0) c 1 0 0110 11rr rrrr 06rr rlc r r(n) r(n+1) r(7) c, c r(0) c 1 0 0111 00rr rrrr 07rr swapa r r(0-3) a(4-7) r(4-7) a(0-3) none 1 0 0111 01rr rrrr 07rr swap r r(0-3) ? r(4-7) none 1 0 0111 10rr rrrr 07rr jza r r+1 a, skip if zero none 2 if skip 0 0111 11rr rrrr 07rr jz r r+1 r, skip if zero none 2 if skip 0 100b bbrr rrrr 0xxx bc r,b 0 r(b) none 1 0 101b bbrr rrrr 0xxx bs r,b 1 r(b) none 1 0 110b bbrr rrrr 0xxx jbc r,b if r(b)=0, skip none 2 if skip 0 111b bbrr rrrr 0xxx jbs r,b if r(b)=1, skip none 2 if skip 1 00kk kkkk kkkk 1kkk call k pc+1 [sp] (page, k) pc none 2 1 01kk kkkk kkkk 1kkk jmp k (page, k) pc none 2 1 1000 kkkk kkkk 18kk mov a,k k a none 1 1 1001 kkkk kkkk 19kk or a,k a k a z 1 1 1010 kkkk kkkk 1akk and a,k a & k a z 1 1 1011 kkkk kkkk 1bkk xor a,k a k a z 1 1 1100 kkkk kkkk 1ckk retl k k a, [top of stack] pc none 2 1 1101 kkkk kkkk 1dkk sub a,k k-a a z,c,dc 1 1 1110 0000 0001 1e01 int pc+1 [sp] 001h pc none 1 1 1110 100k kkkk 1e8k page k k->r5(4:0) none 1 1 1111 kkkk kkkk 1fkk add a,k k+a a z,c,dc 1 ** 1 instruction cycle = 2 main clk
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 30 2004/11/10 v2.6 vii.9_1 code option EM78P5840 code option register 12 11 10 9 8 7 6 5 4 3 2 1 0 ir3 ir2 ir1 ir0 p71s p70s oscm1 oscm0 irc2s mer 1 1 /pot0 bit 0 (/pot0): program rom protect option. if set 1 to the bit, program memory can be access; else if clear this bit , program memory can not be access. bit 3(mer) : memory error recover function 0 ? disable memory error recover function 1 ? enable memory error recovery function if user enable memory error recovery function, mcu will improve effect from environment noise . bit 4 (irc2s): internal rc oscillating frequency (for system clk) select. 0 ? 2m hz 1 ? 4m hz bit5~bit6 (oscm0~oscm1): EM78P5840 oscillating mode select. oscm1 oscm0 oscillating mode 0 0 irc mode 0 1 eric mode 1 x crystal mode bit 7 (p70s): port70 function select bit: oscm1 oscm0 p70s port70 status 0 0 x general purpose io 0 1 x osc input, please cascade resister to avdd 1 x 1 pllc output, please cascade capacitor to avss 1 x 0 general purpose io, pll function will disable bit 8 (p71s): port71 function select bit: 0 ? /reset pin selected.. 1 ? general purpose input po rt ?port71? selected bit 9~ bit12 (ir0~ir3): by setting ir0~ir3, irc mode ?s oscillating frequency can be adjust. next table show the trimming code table of irc frequency. ir3~ir0 frequency 0000 1.05*f 0001 1.10*f 0010 1.15*f 0011 1.20*f 0100 1.25*f 0101 1.30*f 0110 1.35*f 0111 1.40*f 1000 0.65*f 1001 0.70*f 1010 0.75*f 1011 0.80*f 1100 0.85*f 1101 0.90*f 1110 0.95*f 1111 1.0*f * ?f? means the frequen cy of irc output.
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 31 2004/11/10 v2.6 vii.10 pwm (pulse width modulation) (1) overview in pwm mode, both pwm1 and pwm2 pins produce up to a 10-bit resolution pwm output (see. fig.10 for the functional block diagram). a pwm output has a period and a duty cycle, and it keeps the output in high. the baud rate of the pwm is the inverse of the period. fig.11 depicts the relationships between a period and a duty cycle. data bus data bus prd1 comparator comparator tmr1h + tmr1l s rq mux duty cycle match period match p wm 1 t1p0 t1p1 t1en ioc6 prd2 comparator comparator s rq mux duty cycle match period match pwm2 t2p0 t2p1 t2en ioc6 to pwm1if to pwm2if reset reset latch latch 1:2 1:8 1:32 fosc 1:64 1:2 1:8 1:32 fosc 1:64 tmr2h + tmr2l dt2h + dt2l dt2h + dt2l dl2h + dl2l dl2h + dl2l fig.10 the functional block diagram of the dual pwms period duty cycle dt1 = tmr1 prd1 = tmr1 fig.11 the output timing of the pwm (2) increment timer counter (tmrx: tmr1h/twr1l or tmr2h/twr2l) tmrx are ten-bit clock counters with programmable pr escalers. they are designed for the pwm module as baud rate clock generators. tmrx can be read , written, and cleared at any reset conditions. if employed, they can be turned down for power saving by setting t1en bit to 0. (3) pwm period (prdx : prd1 or prd2) the pwm period is defined by writing to the prdx register. when tmrx is equal to prdx, the following events occur on the next increment cycle: ? tmrx is cleared. ? the pwmx pin is set to 1.
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 32 2004/11/10 v2.6 ? the pwm duty cycle is latched from dt1/dt2 to dtl1/dtl2. < note > the pwm output will not be set, if the duty cycle is 0; ? the pwmxif pin is set to 1. the following formula describes how to calculate the pwm period: period = (prdx + 1) * 4 * (1/fosc) * (tmrx prescale value ) where fosc is system clock (4) pwm duty cycle ( dtx: dt1h/ dt1l; dtl: dl1h/dl1l) the pwm duty cycle is defined by writing to the dt x register, and is latched from dtx to dlx while tmrx is cleared. when dlx is eq ual to tmrx, the pwmx pin is cleared. dtx can be loaded at any time. however, it cannot be latched into dtl until the current value of dlx is equal to tmrx. the following formula describes how to calculate the pwm duty cycle: duty cycle = (dtx) * (1/fosc) * (tmrx prescale value) (5) pwm programming procedures/steps load prdx with the pwm period. (1) load dtx with the pwm duty cycle. (2) enable interrupt function by writing iocf pafe0, if required. (3) set pwmx pin to be output by writing a desired value to iocc page0. load a desired value to r5 page3 with tmrx pr escaler value and enable both pwmx and tmrx. (6) timer timer1 (tmr1) and timer2 (tmr2) (tmrx) are 10-bit clock counters with programmable prescalers, respectively. this is designed for the pwm module as baud rate clock generators. tmrx can be read, written, and cleared at any reset conditions. the figure in the next page shows tmrx block diag ram. each signal and block are described as follows:
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 33 2004/11/10 v2.6 data bus data bus prd1 comparator tmr1x mux period match t1p0 t1p1 t1en prd2 comparator tmr2x mux period match t2p0 t2p1 t2en to pwm1if to pwm2if reset reset 1:2 1:8 1:32 f osc 1:64 1:2 1:8 1:32 fosc 1:64 *tmr1x = tmr1h + tmr1l; *tmr2x = tmr2h +tmr2l fig.12 tmrx block diagram ? fosc: input clock. ? prescaler (t1p0 and t1p1): options of 1:2, 1:8, 1:32, and 1:64 are defined by tmrx. it is cleared when any type of reset occurs. ? tmr1x (tmr1h/twr1l):timer x register; tmrx is increased until it matches with prdx, and then is reset to 0. tmrx cannot be read. ? prdx (prd1): pwm period register. when defining tmrx, refer to the related registers of its operation as shown in prescale register. it must be noted that the pwmx bits must be disabled if their related tmrxs are employed. that is, bit 6 of the pwmcon register must be set to ?0?. related control registers(r5 page3) of tmr1 and tmr2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pwm2e pwm1e t2en t1en t2p1 t2p0 t1p1 t1p0 timer programming procedures/steps load prdx with the timer period. enable interrupt function by wr iting iocf page0, if required load a desired value to pwmcon with the tmrx prescaler value and enable both tmrx and disable pwmx.
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 34 2004/11/10 v2.6 vii.11 oscillator the EM78P5840 can be operated in two different oscillator modes, each of them are crystal mode and rc mode. users can select one of them by setting code option. the descript of these two oscillator mode are as below: (1) crystal mode: for crystal mode operation, one crystal and tow capacitanc es is needed for external circuit. in this mode, eftp5840 can be run in three active m ode include normal mode, green mode and sleep mode. the advantages of this mode are low power consumption (in green mode) and with more precise main clk. next figure show the application circuit of crystal mode. pin xin and pin xout can be connected with a crystal directly to generate oscillation. by clear code option?p70s? to 0, port70 can switch to general io (disable pll function and EM78P5840 can not active on normal mode); /reset pin can switch to port71 if clear ?p71s? to 0. xin efhp5840 xout fig 13: application circuit of crystal mode reset operation normal mode green mode sleep mode (cpu stop) reset release reset reset pllen bit = 0 pllen bit = 1 ra page0 bit7 = 0 & run"slep" reset irc1 : on 32k : oscillating pll : turn off irc1 : on 32k : oscillating pll : turn on irc1 : on 32k : un-active pll : turn off fig 14: the relative of crystal mode?s normal, green and sleep mode
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 35 2004/11/10 v2.6 (2) irc mode: for some applications that do not require precise timing calculation, the rc oscillator could offer users with an effective cost savings. eftp5840 offer a versatile internal rc mode with default frequency value of 4m and 2mhz. in this mode, pllc, xin, xout and /reset pins can defined to general purpose io. the irc frequency will drift with the variation of voltage, temperature and process: the frequency deviation of irc mode: internal rc freq range (before adjust ir0~ir3) (ir0~ir3 = 1111) freq range (after adjust ir0~ir3) 4m hz 2.8m ~ 5.2m 3.6m ~ 4.4m 2m hz 1.4m ~ 2.6m 1.8 m ~ 2.2m *the frequency of irc output can be adjust by setting ir0~ir3 in code option. by setting ir0~ir3, the frequency deviation can be compensation. please refer to code option to detail. in irc mode, port60, port61 and port70 are defined to bi-direction io. by clearing p71s in code option to 0, /reset pin can also switch to input pin (port71). in irc mode, only two active modes can be achieved, please refer to next figure to detail. (3) eric mode: eric mode is equipped with an internal capacitor and an ex ternal resistor (connected to vdd). the internal capacitor functions as temperature compensator. in order to obtain more accurate frequency, a precise resistor is recommended. nevertheless, it should be noted that the frequency of the rc oscillator is influenced by the supply voltage, the values of the even by the operation temperature. moreover, the frequency also changes slightly from one chip to another due to the manufacturing process variation. besides, the package types, and the way the pcb is layout, have certain effect on the system frequency. about the application is as below: the frequency deviation of eric mode: internal c, external r freq range 4m hz (r=51k) 3.5m ~ 4.4m 2m hz(r=100k) 1.8m ~ 2.2m eric EM78P5840 vdd r fig 15: application circuit of eric mode eric?s oscillating frequency will base on irc2?s clk (determined on code option ?irc2s?). for example, if irc2s = 0, irc2?s oscillating frequency is 2m hz. at this time, by adjusting r, system clk will be changed. but the system clk will always greater than 2m. that is to say, system clk can only be adjusted between 2m to 6m. next two table show the corresponding between system oscillating clk and the value of external resister. the corresponding between system oscillating clk and the value of external resister frequency (hz) external resister (ohm) operating voltage (vdd) 6m 34k 3.0 ~5.5 v 5m 41k 2.8 ~5.5 v 4m 51k 2.5 ~5.5 v 3.58m 57k 2.2 ~5.5 v 2.1m 97k 2.2 ~5.5 v *only 2 types active mode (normal mode and sleep mode) are permitting in rc mode.
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 36 2004/11/10 v2.6 reset operation normal mode sleep mode (cpu stop) reset run"slep" reset irc1 : on pll : turn off irc1 : on pll : turn off erc or irc2 : on erc or irc2 : on fig 15: the relative of irc and eric mode?s normal and sleep mode vii.12 power on considerations any micro-controller is not guaranteed to start to operate properly before the power supply stabilizes at its steady states. EM78P5840 power on reset voltage range is 1.6v ~ 2.0v. under customer application, vdd must drop to below 1.6v and remains off for 10us before power can be switched on again. this way, EM78P5840 will reset and work normally. the extra external reset circuit w ill work well if vdd can rise at very fast speed (50ms or less). however, under most cases wh ere critical applications are involved, extra devices are required to assist in solving the power-up problems. vii.13 external power on reset circuit by setting code option ?p71s? to 1, /reset pin is select ed. next figure is an external rc to produce the reset pulse. the pulse width should be kept long enough for vdd to reach minimum operation voltage. the diode d acts as a short circuit at the moment of power down . the capacitor c will discharged rapidly and fully. vdd /reset r c d fig 15: external power on reset circuit 1
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 37 2004/11/10 v2.6 por reset voltage is influenced in pr ocess or temperature. for some appli cation, a constant reset voltage is important. next circuit will support a adjust reset voltage . by adjusting r41 and r46, por reset voltage will be a constant (vpor) and the potential on /reset pin will drop to 0 when vdd dr op to below vpor. next plot show the relative between vdd and vpor. when r41 = 3.9m ohm and r46 = 910k ohm, /reset will keep to 0 if vdd is below 2.24v and will active after vdd upper to 2.1v. c31 104 r42 2m2 r43 330k s10 reset vdd r44 22m r41 3m9 reset q3 c1815 q2 c1815 r46 910k fig 16: external power on reset circuit 2 2.24v 2.1v vdd t vdd /reset fig 17: the relative between vdd and vpor
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 38 2004/11/10 v2.6 viii. absolute operation maximum ratings rating symbol value unit dc supply voltage vdd -0.3 to 6 v input voltage vin -0.5 to vdd +0.5 v operating temperature range ta 0 to 70 j ix. dc electrical characteristic (ta = 25 c, avdd=vdd=5v 5%, vss=0v) parameter symbol condition min typ max unit input leakage cu rrent for input pins iil1 vin = vdd, vss 1 a input leakage current for bi- directional pins iil2 vin = vdd, vss 1 a input high voltage (except p71) vih 2.5 v input low voltage (except p71) vil 0.8 v p71 input high voltage vih 2.0 v p71 input low voltage vil 0.8 v input high threshold voltage viht /reset, tcc 2.0 v input low threshold voltage vilt /reset, tcc 0.8 v clock input high voltage vihx osci 3.5 v clock input low voltage vilx osci 1.5 v output high voltage for portc1~portc2 voh1 ioh = -6ma 2.4 v output high voltage for port60~port67; port7 voh2 ioh = -10ma 2.4 v output high voltage for port9 voh3 ioh = -15ma 2.4 v output low voltage for portc1~portc2 vol1 ioh = 6ma 0.4 v output low voltage for port60~port67; port7 vol2 ioh = 10ma 0.4 v output low voltage for port9 vol3 ioh = 15ma 0.4 v pull-high current iph pull-high active input pin at vss -10 -15 a power down current (sleep mode) isb1 all input and i/o pin at vdd, output pin floating, wdt disabled 1 4 a low clock current (green mode) isb2 clk=32.768khz, all analog circuits disabled, all input and i/o pin at vdd, output pin floating, wdt disabled 25 35 a operating supply current (normal mode) icc1 /reset=high, clk=3.582mhz, all analog circuits disabled, output pin floating 1.5 2.5 ma
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 39 2004/11/10 v2.6 xi. ac electrical characteristic cpu instruction timing (ta = 25 c, avdd=vdd=5v, vss=0v) parameter symbol condition min typ max unit input clk duty cycle dclk 45 50 55 % instruction cycle time tins 32.768khz 3.582mhz 60 550 us ns device delay hold time tdrh 16 ms tcc input period ttcc note 1 (tins+20)/n ns watchdog timer period twdt ta = 25 c 16-30% 16 16+30% ms note 1: n= selected prescaler ratio. adc characteristic (vdd = 5v, ta = +25 c, for internal reference voltage) parameter symbol condition min typ max unit upper bound offset voltage vofh 44 52.8 mv lower bound offset voltage vofl 32 38.4 mv *these parameters are characterized bu t not tested. * about adc characteristic, please refer to next page. timing characteristic (avdd=vdd=5v,ta=+25 c) description symbol min typ max unit oscillator timing characteristic crystal start up 32.768khz tosc 400 1500 ms 3.579mhz pll 5 10 us timing characteristic of reset the minimum width of reset low pulse trst 3 us the delay between reset and program start tdrs 18 ms
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 40 2004/11/10 v2.6 vdd osc power on reset /reset tdrs toscs program active tdrs trst the relative between osc stable time and power on reset EM78P5840 operation voltage(x axis ? min vdd ; y axis ? main clk): 5.5 mhz v 14.3 3.6 3.58 2.2 fig.18 the relative between operating voltage and main clk
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 41 2004/11/10 v2.6 em785840?s 10 bit adc characteristic em785840 build in 10 bit resolution, multi channel adc fu nction. in ideal, if adc?s reference voltage is 5v, the adc?s lsb will be 5v/1024. but in practical, for some physics or circuit?s character, some un-ideal will effect the converter result. as the next figure, offset voltage will reduce ad?s co nverter range. if ad?s input voltage less than vofl, adc will output 0; in opposition, if input voltage is larger than (vdd -vofh), adc will output 1023. that is to say the physics ad converter range will replace by (vdd-vof h+lsb-vofl+lsb). if we defined th at vrb = vofl ? lsb and vrt = vdd- vofh+lsb, the physics lsb is: lsb = (vrt - vrb) / 1024 = (vdd ? (vofh+vofl) ) / 1022 for real operating, please think about the effect of ad?s offset voltage. if converter the range of (vrt - vrb), the ad converter?s opposite result will be prcised. 0v vdd min. input for adc output = 1023 10-bit adc (for 10-bit adc, internally it takes this range to average 1024 steps) vofl vofh vrb vrt min. input for adc output = 1 fig.19 the relative between adc and offset voltage
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 42 2004/11/10 v2.6 xii. timing diagrams fig.20 ac timing ins
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 43 2004/11/10 v2.6 xiii. EM78P5840 otp rom burning pins one time programmable rom burner pin otp pin name mask rom pin name p.s. vdd avdd vpp /reset dinck p65 aclk p64 pgmb p63 oeb p62 data p73 gnd avss
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 44 2004/11/10 v2.6 appendix: package spec of EM78P5840/5841/5842 EM78P5840m EM78P5840p
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 45 2004/11/10 v2.6 em78p5841m em78p5841p
EM78P5840/5841/5842 8-bit micro-controller _______________________________________________________________________________________________________________________________ ___________________________________ * this specification is subject to change without notice. 46 2004/11/10 v2.6 em78p5842m em78p5842p

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